(a) Field of the Invention
The present invention relates to a buffer circuit and an active matrix display using the same.
(b) Description of the Related Art
Active matrix displays, image sensors, and semiconductor memories use a shift register circuit and a buffer circuit to supply scan signals. When the shift register circuit has a large load or capacitance, a buffer circuit is installed between the shift register circuit and the load. The usage of the buffer circuit increases the magnitude of the current for charging and discharging the load, thereby increasing operation rates. If the buffer circuit becomes larger according to the load size, the capacitance at an input end of the buffer circuit increases, thereby reducing the operation rates.
Accordingly, the buffer circuit usually has a plurality of inverters coupled in series as shown in FIG. 1, and the inverters coupled in series gradually increase the magnitude of the current, thereby increasing the operation rates. The number of the inverters is generally within four.
Referring now to FIG. 2, a conventional buffer circuit will be described in detail.
As shown, the conventional buffer circuit includes two inverters respectively including two PMOS transistors M1 and M2, and two PMOS transistors M3 and M4. Sources of the transistors M1 and M3 are coupled to a high power source that supplies a high-level voltage VDD, and drains of the transistors M2 and M4 are coupled to a low power source that supplies a low-level voltage VSS. A drain of the transistor M1 and a source of the transistor M2 are coupled together, and their coupling node is coupled to the gate of the transistor M3. A drain and a gate of the transistor M2 are coupled together; and a drain and a gate of the transistor M4 are coupled together. In other words, each of the transistors M2 and M4 is diode-connected. Also, the drain of the transistor M3 and the source of the transistor M4 are coupled together, and their coupling node is defined to be an output Vout of the buffer circuit.
In this instance, when a signal Vin input applied to a gate of the transistor M1 is high-level, a gate of the transistor M3 becomes low-level because of the transistor M2. Hence, the transistor M3 is turned on. Therefore, the output Vout of the buffer circuit is determined by an on-resistance ratio of the transistors M3 and M4 to be lower than VDD. Since the transistors M3 and M4 are concurrently turned on, a static current flows through the transistors M3 and M4, thereby increasing power consumption.
When the signal Vin input to the gate of the transistor M1 is low-level, a high-level voltage, based on the on-resistance ratio of the transistors M1 and M2, of less than VDD is input to the gate of the transistor M3. Hence, the transistor M3 is turned off, thereby reducing the output voltage Vout, and a source-gate voltage at the transistor M4 accordingly reduces. Therefore, the load driving current is decreased. In this instance, when the output voltage Vout reaches VSS+|VTH4| (VTH4 is the threshold voltage of the transistor M4), current rarely flows to turn off the transistor M4, and the output voltage Vout is fixed to be VSS+|VTH4|. Since the transistors M1 and M2 are concurrently turned on, a static current flows through the transistors M1 and M2.
In order for the buffer circuit to have sufficient driving performance even if the source-gate voltage reduces, a channel width of the transistor M4 should be increased. When the channel width increases, the on-resistance of the transistor M4 reduces, thereby decreasing the high-level output of the buffer circuit, and therefore, the channel depth of the transistor M3 should be further increased.
As described, the buffer circuit shown in FIG. 2 has a high-level output of less than VDD, and a low-level output of greater than VSS. Also, when an input is high-level, a static current flows through the inverter in the second stage, and when the input is low-level, a static current flows through the inverter in the first stage. As a result, the power consumption increases due to the static current flowing through inverters which is great for the second stage according to characteristics of the buffer circuit.